Cascaded Connection of Single-Phase & Three-Phase Multilevel Bridge Type Inverter
Abstract: The function of this work is to minimize total harmonics distortion and number of switch and improve level in output voltage waveform. In conventional method, needed five H-bridge units to used 11-echelon inverter but in this proposed method for a 28-echelon cascaded H-bridge multilevel inverter required only three H-bridge unit per phase.

Authors: Mukesh Kumar Sharma, Ram Swaroop, Mukesh Kumar Kuldeep

File Name: 50100-16-128.pdf
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3-Dimensional (3D) ICs: A Survey
Abstract: VLSI circuits are scaled to meet improved functionality, performance and lower power dissipation at low cost, which in turn has some serious problems for the semiconductor industry.3-dimensional integrated circuits(3D ICs) can provide solutions for these problems.

Authors: Lavanyashree B.J

File Name: 50100-16-151.pdf
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REVIEW :- LOW POWER DOUBLE TAIL COMPARATOR BY CLOCK GATING
Abstract: The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In the previous paper[19], an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double tail comparator is modified for low-power and fast operation even in small supply voltages.

Authors: Balmit Singh, Dinesh Chand Gupta

File Name: 50100-16-120.pdf
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