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Research Article

A Novel Approach for 5 Stage Pipelined RISC Processor

Suranjit Kosta  ·  Ankit Pandit

IJDACR Vol.7 No.10 (May 2019) ISSN 2319-4863 Open Access Peer Reviewed

Journal

International Journal of Digital Applications and Contemporary Research (IJDACR)

ISSN

2319-4863

Volume / Issue

Vol.7 · Issue 10

Published

May 2019

Access

Open Access

Licence

CC BY-NC-SA 4.0

Authors

Suranjit Kosta Ankit Pandit

Abstract

The proposed research work is the design of a 32 bit RISC (Reduced Instruction Set Computer) processor. The design helps to improve the speed of processor, and to give the higher performance of the processor. It has 5 stages of pipeline viz. instruction fetch, instruction decode, instruction execute, memory access and write back all in one clock cycle. The control unit controls the operations performed in these stages. All the modules in the design are coded in VHDL.

Keywords

RISC SISC Pipeline Processor VHDL

How to Cite

Suranjit Kosta, Ankit Pandit (2019). A Novel Approach for 5 Stage Pipelined RISC Processor. International Journal of Digital Applications and Contemporary Research (IJDACR), Vol.7, Issue 10. ISSN: 2319-4863.

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Article Info

Journal IJDACR
Volume Vol. 7
Issue No. 10
Month May
Year 2019
ISSN 2319-4863
Access Open Access

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