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Research Article

VHDL Implementation of BIST Enabled UART

Manisha Golia  ·  Asst. Prof. Sunil Shukla  ·  Prof. H. R. Singh

IJDACR Vol.4 No.11 (June 2016) ISSN 2319-4863 Open Access Peer Reviewed

Journal

International Journal of Digital Applications and Contemporary Research (IJDACR)

ISSN

2319-4863

Volume / Issue

Vol.4 · Issue 11

Published

June 2016

Access

Open Access

Licence

CC BY-NC-SA 4.0

Authors

Manisha Golia Asst. Prof. Sunil Shukla Prof. H. R. Singh

Abstract

This paper introduces a novel approach of Linear Feedback Shift Resister (LFSR) for Built-in-self-test (BIST) along with 8 bit UART, to overcome testability and data integrity. The complete design is implemented in VHDL and simulated throughout in Modelsim, synthesis is carried out in Xilinx 14.1.

How to Cite

Manisha Golia, Asst. Prof. Sunil Shukla, Prof. H. R. Singh (2016). VHDL Implementation of BIST Enabled UART. International Journal of Digital Applications and Contemporary Research (IJDACR), Vol.4, Issue 11. ISSN: 2319-4863.

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Article Info

Journal IJDACR
Volume Vol. 4
Issue No. 11
Month June
Year 2016
ISSN 2319-4863
Access Open Access

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